NAFEMS Americas and Digital Engineering (DE) teamed up (once again) to present CAASE, the (now Virtual) Conference on Advancing Analysis & Simulation in Engineering, on June 16-18, 2020!

CAASE20 brought together the leading visionaries, developers, and practitioners of CAE-related technologies in an open forum, unlike any other, to share experiences, discuss relevant trends, discover common themes, and explore future issues, including:
-What is the future for engineering analysis and simulation?
-Where will it lead us in the next decade?
-How can designers and engineers realize its full potential?
What are the business, technological, and human enablers that will take past successful developments to new levels in the next ten years?

Resource Abstract

Through silicon via interconnects (TSV) are high performance interconnect technique alternative to wirebond and flipchip for application in 2.5D and 3D IC packaging. TSVs have picked up a lot of momentum in recent years because TSV is a key enabling technology for 2.5D/3D IC stacking, silicon interposer technology, and advanced wafer level packaging (WLP). It passes through a silicon wafer vertically which not only reduces the power consumption but also give a better electrical performance with wider data width and bandwidth owning to its compact size. The product where TSVs are used include MEMS, LED packaging, Memory, Image censors etc. which has application in automotive electronics, consumer electronics, telecommunication, aerospace and defence.



However, thermo-mechanical reliability is a key concern for the growth of the 3D TSV market. This is due to the coefficient of thermal expansion (CTE) mismatch between silicon and conducting material (Cu) which is more than 10 ppm/K and which generates a significant thermal stress due to the heat generated in the ICs. In this present work, a three-dimensional thermo-mechanical finite-element model has been built to analyze the stress/strain distribution in the TSV structures. A fracture mechanics analysis is also performed for the Cu/SiO2 interfacial cracks. An automated workflow is created using ANSYS ACT extension that drastically reduces human error by converting complex manual analysis into an automatic process to identify critical crack and interface delamination locations. The ACT extension also automates the submodeling analysis set up, which reduces the computational expenses for a high-fidelity simulation. The automated workflow comprises of failure location identification, submodel domain specification, material mapping, mesh refinement, loads and boundary conditions transfer, crack insertion and postprocessing. The ACT application is not limited to TSV cracking analysis and can be used in any other scenario to create submodel analysis set up for any high-fidelity solution with an optional downstream fatigue and fracture analysis. This workflow can help analyst to swiftly create highly precise models, rapidly determine the optimal solution, identify problematic parts and reduce significant overall development time.